1. Field of the Invention
The present invention relates to circuit techniques for rapidly and efficiently correcting read and write data errors in a digital semiconductor memory.
2. Brief Description of the Related Art
In very high density semiconductor memory products such as Flash memory, DRAM, or SRAM, exhaustive testing and repair procedures after fabrication are essential to ensure the proper operation of every memory location under worst possible conditions and can account for a significant portion of the total production cost.
The producers of semiconductor memory must deal with the problems of process yield, the number of devices that operate according to specifications in a given production lot. Flash memory manufacturers must deal with problems arising from cell wear-out as well. As memory cell defects are the most common Flash failure mechanism, Flash memory designers have typically attempted to increase the yield with redundancy; that is, spare rows and columns are built into the memory array and any defective elements are substituted with a redundant one. The larger the device, the more complex it is to manage the redundancy, as external registers are necessary to store the failed element addresses. Exhaustive testing under a full range of test conditions is required after fabrication to identify all of the faulty cells. The post-fabrication testing procedure alone comprises about 50% of the total production cost. Furthermore, post-fabrication testing cannot account for cells that wear out later on, as some Flash memory cells are weaker than others and have a limited lifetime.
Assuming that an un-repaired Flash memory has a defective cell probability of 10−6 for each individual cell and assuming that the errors occur independently of each other, (although that may not actually be true on a real chip), one can envision the scope of problems with un-repaired Flash memory. Given that a typical NOR Flash memory fabricated in 0.13-μm technology has a random access time of 70 ns and accesses 16 bits at a time, an un-repaired memory matrix with a fault probability of 10−6 per cell would have about 5.9×109 errors per month, reading continuously.
Static redundancy can correct for errors caused by post-fabrication oxide defects, but does not correct for soft errors or defective cells that arise from memory wear. One possible alternative to static redundancy that can correct for all three types of errors is the use of error-correcting codes. Applying error-correcting codes to semiconductor memory is a fairly new concept, and has not yet been widely implemented in hardware.
Because memory accesses in certain types of semiconductor memory are expected to occur in a short amount of time, fast decoding circuits are necessary in order to implement error-correcting codes. NOR Flash has access times of about 70 ns in 0.13 μm technology. The access latency of DRAM is about 50 ns, and the access latency of SRAM is about 5 ns.
A Hamming code is a linear error-correcting code that uses parity to detect errors. Hamming codes are most popular for correcting errors in main memory, because they have simple computational requirements and can be decoded using minimal circuitry. This scheme allows one bit in the word to be corrected, and it can detect double bit errors but is unable to correct events where more than one bit in the word is in error.
In “A Compact On-chip ECC for Low Cost Flash Memories,” IEEE Journal of Solid-State Circuits, 22, 5 (1997), Tanzawa, et al. implemented a decoder for the (522, 512) Hamming scheme, targeted towards NAND Flash. The circuit was implemented in 0.4-μm technology and optimized for low area overhead. Data bits are processed completely in series for a decoding time that is approximately equivalent to the latency for reading 512 bits in series. The total latency for accessing 512 serial bits in NAND Flash in 0.4-μm technology is around 15 μs. Scaling the design linearly for an equivalent circuit in 0.18-μm technology would indicate an estimated latency of 6.75 μs. However, Tanzawa, et al. designed their Hamming decoder for NAND Flash, and therefore area and energy costs were weighted more heavily than access delays.